A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to FIG. 1, a photolithograpy system 100 is used for patterning integrated circuit structures on a semiconductor wafer 102. In the photolithography system 100, a reticle 104 has a pattern of polygons thereon to be patterned onto the semiconductor wafer 102. Light from a light source 106 is illuminated through the pattern of polygons on the reticle 104 onto the semiconductor wafer 102. In addition, a lens system 108 is used within the photolithography system 100 to typically reduce the image of the pattern of polygons on the reticle 104 onto the semiconductor wafer 102. The pattern of polygons on the reticle 104 are typically opaque to the light from the light source 106.
A photoresist material on the semiconductor wafer 102 is cured when light from the light source 106 reaches the photoresist material and is not cured otherwise. When the photoresist material is then developed, cured photoresist material may be etched away while the uncured photoresist material remains, and the remaining uncured photoresist material may further act as a mask for etching away exposed material deposited below the photoresist material. Thus, when the light from the light source 106 does not reach the semiconductor wafer 102 for the pattern of opaque polygons on the reticle 104, the pattern of polygons on the reticle 104 is transferred to the photoresist material on the semiconductor wafer 102. Such a photolithography system 100 is known to one of ordinary skill in the art of integrated circuit fabrication.
As the dimensions of integrated circuit structures are constantly scaled down such that a desired dimension of an integrated circuit structure is smaller than the wavelength of the light from the light source 106 within the photolithography system 100, the shape and dimensions of the structure formed on the semiconductor wafer 102 is no longer that expected from the design of the pattern of polygons on the reticle 104. For example, referring to FIG. 2, assume that a polygon 110 is designed on the reticle 104 for a rectangular shape to be patterned on the semiconductor wafer 102 within the photolithography system 100. When the width of the polygon 110 is smaller than the wavelength of the light from the light source 106 within the photolithography system 100, the actual polygon 112 patterned onto the semiconductor wafer 102 is different from the expected polygon 110.
Typically, the polygon 110 on the reticle 104 acts as a low-pass filter when the width of the polygon 110 is smaller than the wavelength of the light from the light source 106 such that the corners of the actual polygon 112 become more rounded than desired and the length of the actual polygon 112 become shorter than desired, as known to one of ordinary skill in the art of integrated circuit fabrication. Such non-linear distortions of the actual polygon 112 results from optical diffraction of the light from the light source 106 and resist effects in pattern transfer when the width of the polygon 110 is smaller than the wavelength of the light from the light source 106, as known to one of ordinary skill in the art of integrated circuit fabrication. The nature of the non-linear distortions of the actual polygon 112 also depends on the density, size, and location of nearby polygon features, as known to one of ordinary skill in the art of integrated circuit fabrication.
The wavelength of light from the light source 106 is currently approximately 250 nanometers. However, device dimensions are now desired to be below 200 nanometers. Referring to FIG. 3, to over-come such non-linear distortions, the patterned polygons of the reticle are perturbed with addition of OPC (optical proximity corrections), as known to one of ordinary skill in the art of integrated circuit fabrication. In the example of FIG. 3, such OPC (optical proximity corrections) includes structures that are added to the pattern of polygons of the reticle to negate the non-linear distortions.
Referring to FIG. 3, assume that the initial reticle 104 without any OPC (optical proximity corrections) includes a first polygon 122 and a second polygon 124. Then, OPC (optical proximity corrections) structures are added as perturbations to the polygons 122 and 124 of the initial reticle 104 to result in a perturbed reticle 130. Example OPC (optical proximity corrections) structures include “dog-ears” 132 (i.e., opaque squares or rectangles) added to outside corners of the polygons, “cut-outs” 134 (i.e., transparent squares or rectangles) added to inside corners of the polygons, and long-line embellishments 136 (i.e., transparent rectangles) added to sides of relatively long polygons. When the perturbed reticle 130 is used within the photolithograpy system 100, such OPC (optical proximity corrections) structural perturbations added to the polygons 122 and 124 negate the non-linear distortions such that the pattern transferred to the semiconductor wafer 102 is closer to the desired pattern of polygons even when the dimensions of the polygons are smaller than the wavelength of light from the light source 106, as known to one of ordinary skill in the art of integrated circuit fabrication.
However, different OPC (optical proximity corrections) have different effects on the polygons patterned onto the semiconductor wafer. For example, different shapes, sizes, and locations of the OPC (optical proximity corrections) structures added to perturb the polygons of the reticle have different effects on the polygons patterned onto the semiconductor wafer. Thus, a determination of optimum OPC (optical proximity corrections) is desired for achieving polygons patterned onto the semiconductor wafer that are closest to the desired pattern of polygons.
In the prior art, the optimum OPC (optical proximity corrections) are determined by manual trial and error. Various reticles with different OPC (optical proximity corrections) structures added are used and the resulting polygons patterned onto the semiconductor wafer are visually examined to determine the optimum OPC (optical proximity corrections). However, such a manual determination by trial and error is tedious and prone to human error as such a process is repeated for different integrated circuit processes and different photolithography systems.
Thus, a mechanism is desired for efficiently and accurately determining optimum OPC (optical proximity corrections).